1. Field of the Invention
The present invention generally relates to data communication, and more particularly to data communication between a data carrier device and a data carrier driving device.
2. Related Background Art
FIG. 15 is a diagram showing the schematic configuration of a conventional data communication system. In the conventional configuration, when a data carrier device 802 and a control device (hereinafter also referred to as a data carrier driving device) 801 perform data communication, four contacts for a power source VIN, ground GND, a clock signal CLK and a data signal DATA are severally provided to connect the data carrier device 802 and the control device 801 with each other.
Moreover, a configuration enabling two-way data communication with two contacts in a system in which a control device and a data carrier device perform data communication with the object of miniaturizing the system is stated in, for example, Japanese Patent Application Laid-Open No. 2003-69653.
Only a data carrier device 900 in the configuration of the control device and the data carrier device which enables the two-way data communication with the two contacts and is stated in Japanese Patent Application Laid-Open No. 2003-69653 is shown in FIG. 16. Here, the operation of the data carrier device 900 shown in FIG. 16 is described using a timing chart, shown in FIG. 17, of the data carrier device 900 of the FIG. 16.
The data carrier device 900 has only two terminals of A terminal A and A terminal B, and performs data communication with the control device with these two terminals. To the terminal A, a pulse voltage VA is input. The pulse voltage VA has a certain fixed frequency and a certain fixed duty ratio. The high levels (hereinafter referred to as H levels) of the voltage amplitudes of the pulse voltage VA include two-step control of V1 and V2, and the low level (hereinafter referred to as an L level) of the pulse voltage VA is ground (GND) potential. Then, to the other residual terminal B, a pulse voltage VB is input. In comparison with the pulse voltage VA, the pulse voltage VB has the same voltage amplitudes as those of the pulse voltage VA, and is in a reversed phase relation with the phase of the pulse voltage VA. In the data carrier device 900, into which these pulse voltages VA and VB are input, a clock generator circuit 901 generates a clock signal CLK which synchronizes with the frequencies of these two pulse voltages VA and VB. Moreover, a VA+VB circuit 902 rectifies these two pulse voltages VA and VB to generate a constant voltage having two-step control V1 and V2 of the H levels of the voltage amplitudes and GND potential of the L level as shown in FIG. 17. An amplitude discriminator circuit 903 detects the difference voltage of the voltage amplitudes of the H level to generate a data signal DATA. The clock signal CLK and the data signal DATA are supplied to an internal circuit 904, the other component of the data carrier device 900, and the data to be communicated is generated.
Moreover, as data communication means from the data carrier device 900, the impedance conversion between the terminal A and the terminal B is performed by shorting the terminal A and the terminal B with each other or the like. And, the control device detects the impedance conversion to receive the data from the data carrier device 900.
However, there are the following problems in the data carrier device mentioned above.
First, because the above-mentioned prior art which is shown in FIG. 15 and is provided with four contacts for the power source VIN, the ground GND, the clock signal CLK and the data signal DATA needs four contacts, the prior art is not suitable for the miniaturization of the system.
Moreover, the data carrier device 900 shown in FIG. 16 operates satisfactory when there is no phase difference at all between the pulse voltage VA input into the terminal A and the pulse voltage VB input into the terminal B. However, because sections in which the two pulse voltages VA and VB together take the L level or together take the H level are produced, sections to which no electric power is supplied to the data carrier device 900 are produced. Hence, there is a possibility of producing a problem of securing the operational stability of the data carrier device 900. In the actual system configuration, there is a possibility of producing the delay of an internal circuit of the control device and a difference of impedance owing to the resistance values and the parasitic capacitance of the wiring from the control device to the terminal A of the data carrier device 900 and the wiring from the control device to the terminal B of the data carrier device 900. Consequently, it is very difficult not to produce any phase differences between the pulse voltage VA input into the terminal A and the pulse voltage VB input into the terminal B.
Moreover, another configuration of the control device and the data carrier device which makes it possible to perform the two-way data communication with two contacts is disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 2003-69653 besides the system shown in FIG. 16. That is, a fixed voltage which has two voltage values composed of the H level of V1 in voltage amplitude and the L level of V2 in voltage amplitude is input into the terminal A of the data carrier device, and the GND potential is input into the terminal B thereof. Then, by detecting the voltage difference between the voltages VA and VB to generate a data signal. Furthermore, there is a method of generating a clock signal in the data carrier device independently of the signal from the control device. However, because the control device and the clock signal of the data carrier device cannot be synchronized with each other by this method, the method has a problem of the complexity of the data communication method.
Moreover, there is the following method as a further method cited in the Japanese Patent Application Laid-Open No. 2003-69653. That is, the duty ratio of a pulse voltage VA input into the terminal A of the data carrier device is fixed to be 50%, and the frequency of the pulse voltage is variably controlled. To the terminal B, a pulse voltage VB having a reversed phase to the phase of the pulse voltage VA is input. By detecting the frequency value, the data signal is generated. Furthermore, there is a method of generating a clock signal synchronizing with the input frequency. However, in this method, the sections in which electric power is not supplied to the data carrier device are produced in the case where a phase difference occurs between the pulse voltages VA and VB. Consequently, the method has a problem of the difficulty of securing the operational stability of the data carrier device.
Moreover, there is the following method as a still further method cited in the Japanese Patent Application Laid-Open No. 2003-69653. That is, a pulse voltage which has the voltage amplitudes of the H level of V and the L level of either of V1 and V2 and a duty ratio of 50% is input into the terminal A of the data carrier device, and the GND potential is input into the terminal B. Then, a data signal is generated by detecting the voltage difference between the voltages V1 and V2 of the L level. Thus, the method is one generating the clock signal synchronized with the input frequency. However, in this method, the voltage difference between the voltages V1 and V2 of the L level becomes a minute value, and the detection means having very high precision becomes necessary. Consequently, the method has a problem such that the system becomes expensive.
Moreover, there is the following as the data communication means from the data carrier device cited in the Japanese Patent Application Laid-Open No. 2003-69653. That is, the impedance conversion between the terminal A and the terminal B is performed by shorting the terminal A and the terminal B with each other, and the impedance conversion is detected on the control device side. Thus, the method is one receiving the data signal from the data carrier device. However, by this method, the short circuit of the power source of the internal circuit is caused, and the method has a further problem of the difficulty of the operational stability of the data carrier device.
As still further prior art, a still further configuration of the control device and the data carrier device enabling the two-way data communication with two contacts, which configuration is stated in the Japanese Patent Application Laid-Open No. 2003-69653, is shown in FIG. 18. FIG. 18 shows only data carrier device 900. Using the timing chart of the data carrier device 900 of FIG. 18 shown in FIG. 19, the operation of the data carrier device 900 shown in FIG. 18 is described.
The data carrier device 900 has only two terminals of an A terminal and a B terminal, and performs the data communication with the control device with these two terminals. A pulse voltage VA having a fixed duty ratio of 50% and a frequency controlled pursuant to the two-step control is applied to the A terminal. There are the frequencies of one having a period of f1 and the other one having a period of f2. A pulse voltage VB having a phase reversed to that of the pulse voltage VA input into the B terminal is input into the B terminal. A frequency discriminator circuit 903 generates a data signal DATA by detecting the frequency value, and generates the data to be communicated by supplying the data signal DATA to the other circuit, the internal circuit 904 to perform the communication with the control device. The clock generator circuit 901 generates the clock signal CLK. A rectifier circuit 905 performs rectification.
However, the data carrier device shown in FIG. 18 has the following problem.
The clock generator circuit 901, which generates the clock signal CLK necessary for the operation of the internal circuit from the pulse voltage VA input into the A terminal, can be realized in a simple circuit configuration in case of generating the clock signal CLK having the frequency synchronized with the frequency of the pulse voltage VA.
However, in the case of the data carrier device 900 shown in FIG. 18, the frequency of the pulse voltage of the pulse voltage VA input into the A terminal is variably controlled for the generation of data signal. Consequently, the frequency of the clock signal CLK necessary for the operation of the internal circuit to be generated varies in response to the data signal DATA. At this time, because the frequency of the clock signal CLK input into the internal circuit 904 differs, the transient characteristic of the internal circuit 904 differs according to each frequency. Consequently, in order to configure the internal circuit 904 stabilized over the input frequency range, there is a problem such that a circuit becomes complicated and a system becomes expensive.